Memory cell array

ABSTRACT

A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/877,313, filed on Jun. 25, 2004 now U.S. Pat. No. 7,773,442, entitled “Memory Cell Array Latchup Prevention.”

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to integrated circuits and, more specifically, complementary metal oxide semiconductor (CMOS) memory circuits that are configured to be free or immune from latch up.

2. Description of the Related Art

The following descriptions and examples are given as background information only.

Integrated circuit semiconductor devices using CMOS technology inherently contain parasitic bipolar pnp and npn transistors in the structure of p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) devices. For example, in a structure of a n-well CMOS circuit, a parasitic pnp bipolar transistor may be formed when a source/drain region of a PMOS device acts as an emitter, the n-well of the PMOS device acts as a base, and a p-type doped substrate acts as the collector. In addition, a parasitic npn bipolar transistor may be formed when a source/drain region of the NMOS device acts as an emitter, a substrate tie of the NMOS device acts as a base, and the n-well of the PMOS device acts as the collector. Since the parasitic bipolar transistors are connected through the n-well of the PMOS device (serving as the collector of the npn bipolar transistor and the base of the pnp bipolar transistor) and through p-type doped substrate (serving as the collector of the pnp bipolar transistor and the base of the npn bipolar transistor), the transistors interact electrically to form a pnpn diode structure equating to a silicon controlled rectifier (SCR).

A disadvantage of forming an SCR within a CMOS circuit is that it allows a low-resistance path between power supply buses to form, which in turn allows high amounts of current to flow through the circuit. In some cases, the current through the circuit can be amplified to a level at which one or more memory cells are in a state where they cannot be switched. In particular, internal voltages across the anode and cathode of an SCR which exceed a breakover or trigger voltage can cause junctions within the bipolar transistors of the circuit to become forward-biased. As a result, the SCR enters into a low impedance state with the possibility of a resultant high current. The low impedance state can be maintained indefinitely if a minimum holding current can be supplied to the circuit. As a consequence, the memory cells of the circuit may be restricted from switching and may lose their data. The SCR, in such a state, is commonly referred to as being latched up and, thus, the phenomenon of inducing a circuit into such a state is commonly referred to as “latch up.”

As device dimensions continue to decrease and device density increases, the latch up phenomenon becomes more prevalent. In particular, the closer NMOS and PMOS devices are fabricated relative to each other, the breakover voltage needed to forward-bias junctions within pnpn diode structures created therefrom as well as the minimum holding current needed to maintain a circuit in such a state decrease. As such, various techniques for controlling latch up in CMOS circuits have been proposed and are used in the microelectronics fabrication industry. For example, one method for controlling latch up in CMOS circuits involves incorporating well and/or substrate taps within a circuit to respectively reduce well and substrate resistances. In order to realize the benefit of such a technique, the taps are generally fabricated within each cell of a memory array. As a consequence, cell size is undesirably increased and the objective to increase memory cell density is hindered. In addition, the fabrication of contacts is sensitive to processing parameters of the circuit, such as mask alignment, for example.

Another technique used in the microelectronics industry for controlling latch up in CMOS circuits includes the formation of low resistance well regions having a varied doping profile within the substrate of the circuit. Such a technique is used to reduce the current-gain product of the parasitic bipolar transistors of the CMOS circuit and retard minority carrier injection into active junctions of the device. The formation of low resistance well regions, however, induces higher junction capacitance, which may undesirably increase the threshold voltage at which devices operate. Higher threshold voltages lead to decreased circuit speeds, which is contrary to the industry objective to increase processing speeds within circuits. Moreover, the formation of low resistance well regions does not completely eliminate the formation of latch up. In addition, well region fabrication is sensitive to processing parameters of the circuit, such E mask alignment and processing temperatures, for example. In particular, the placement of well regions within a circuit is directly dependent on the correct alignment of masks with the substrate. Misplacement of well regions may adversely affect the functionality of the device and, in some cases, cause the device to malfunction. In addition, the diffusion of dopants both vertically and horizontally can vary with the temperature, affecting the efficacy of low resistance wells. Furthermore, the activation of dopants to form well regions involves a thermal process, which is an additional restraint for the overall thermal budget of the device.

It would, therefore, be advantageous to develop other manners in which to prevent latch up in CMOS circuits. In particular, it would be beneficial to develop techniques for preventing latch up which do not increase memory cell size, are less sensitive to process variations and do not affect the functionality of the CMOS circuits.

SUMMARY OF THE INVENTION

The problems outlined above may be in large part addressed by a CMOS circuit having one or more current-limiting devices arranged along a power-supply bus and/or a ground bus of the circuit which are configured to prevent latch up within the circuit. More specifically, the one or more current-limiting devices may be configured to maintain a junction of a parasitic pnpn diode structure within the circuit as reverse-biased such that latch up within the circuit may be prevented. More specifically, the one or more current-limiting devices may be configured to prevent end junctions of a parasitic pnpn diode structure from achieving forward biases sufficient or strong enough to forward bias a middle junction of the parasitic pnpn diode structure. A current limiting device arranged along the power-supply bus may include a resistor or a p-channel field-effect transistor pass gate. Alternatively, a current limiting device arranged along the ground bus may include a resistor or an n-channel field-effect transistor pass gate. In either case, IS the one or more current-limiting devices may be specifically configured to prevent latch up caused by high energy radiation on the circuit. In particular, one or more current-limiting devices may be configured to prevent latch up caused by alpha particles and/or cosmic rays. In addition or alternatively, the one or more current-limiting devices may be configured to prevent latch up caused by current injecting defects within the circuit. Furthermore, the one or more current-limiting devices may be configured to eliminate single event latch up caused by excessive substrate current to the CMOS circuit.

In some cases, one or more current-limiting devices may be arranged along a segment of the power-supply bus that is configured to supply power to all memory cells within the array. In addition or alternatively, one or more current-limiting devices may be arranged along a segment of the power-supply bus configured to provide power to a subset of the memory cells. For example, one or more current-limiting devices may be arranged along a segment of the power-supply bus configured to provide power to a single column or row of the memory cells. In other embodiments, one or more current-limiting devices may be arranged along a segment of the power-supply bus configured to provide power to a block of the memory cells arranged within a plurality of columns and a plurality of rows of the memory cells. In yet other cases, one or more current-limiting devices may be arranged along a portion of a ground bus of the circuit as noted above.

A method for sizing one or more current-limiting devices to prevent latch up within a CMOS circuit is also contemplated herein. In particular, a method is provided which includes creating a current-voltage (I-V) plot of a pnpn diode structure arranged within a first CMOS circuit which does not include a current-limiting device arranged along a power bus of the circuit. The method further includes determining a holding current level from the I-V plot and sizing a current-limiting device which is to be placed along a power-supply or ground bus of a second CMOS circuit having similar design specifications as the first CMOS circuit. In particular, the method may include sizing the current-limiting device such that the current through the second CMOS circuit does not exceed the holding current level. In some embodiments, the method may further include determining a trigger current level from the I-V plot of the pnpn diode structure and sizing the current-limiting device to be placed along the power bus of the second CMOS circuit such that the current through the second CMOS circuit does not exceed the trigger current level. As such, the step of sizing may include selecting a current limiting device having a current-voltage characteristic which intersects the current-voltage plot of the pnpn diode at a level below the holding current level and, in some embodiments, at a level lower than the trigger current.

There may be several advantages for providing the CMOS circuit and method described herein. In particular, a CMOS circuit may be fabricated which is immune or free from latch up. As a result, the reliability of CMOS circuits may be improved. In addition, the inclusion of one or more current-limiting devices along the power-supply bus of a CMOS circuit does not affect write and read operations of the circuit and, therefore, circuit simulation models of circuits do not have change with the incorporation of current-limiting devices. Moreover, the formation of current-limiting devices is not significantly sensitive to fabrications variations. Consequently, incorporating current-limiting devices within a CMOS circuit does not cause a significant variance in the functionality of the device. Another advantage of the inclusion of one or more current-limiting devices with a CMOS circuit is that single even latch up (SEL) caused by excessive substrate current may be completely eliminated, thereby improving the reliability of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

FIG. 1 a depicts an exemplary circuit diagram of a portion of a CMOS circuit having a resistor formed along a power-supply bus of the circuit;

FIG. 1 b depicts an exemplary circuit diagram of a portion of a CMOS circuit having a p-channel resistor pass gate formed along a power-supply bus of the circuit;

FIG. 2 depicts an exemplary circuit diagram of a portion of a CMOS circuit having one or more current-limiting devices formed along a ground bus of the circuit;

FIG. 3 depicts an exemplary circuit diagram of a portion of a CMOS circuit having one or more current-limiting devices formed along both a power-supply bus and a ground bus of the circuit;

FIG. 4 depicts an exemplary structure of a pnpn diode structure;

FIG. 5 depicts a flow chart of a method for sizing a current-limiting device within a CMOS circuit to prevent latch up within the circuit;

FIG. 6 a depicts a graph including I-V plots of a pnpn diode structure and a resistor; and

FIG. 6 b depicts a graph including I-V plots of a pnpn diode structure and a pass gate transistor.

While the invention may include various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Turning to the drawings, exemplary embodiments of CMOS circuits having current limiting devices arranged along power-supply buses and/or ground buses are illustrated. In particular, FIG. 1 a illustrates resistor R_(L) formed along power-supply bus 12 of CMOS circuit 10. FIG. 1 b illustrates p-channel pass gate transistor 26 formed along power-supply bus 22 of CMOS circuit 20. CMOS circuit 30 is shown in FIG. 2 having current-limiting device 36 along ground bus 34 and CMOS circuit 40 shown in FIG. 3 includes current-limiting devices 46 and 48 arranged along power-supply bus 42 and ground bus 44, respectively. Each of the circuits is described in more detail below, particularly in reference to the arrangement and type of current-limiting devices included therein. In addition to the current-limiting devices, the CMOS circuits depicted in FIGS. 1 a-3 include parasitic resistances Rw and Rs, respectively referring to parasitic resistances of the well regions and substrate used to form complementary sets of PMOS and NMOS transistors within the circuits.

As shown in FIGS. 1 a-3, the CMOS circuits include parasitic bipolar transistors PNP and NPN, The parasitic bipolar transistors are the result of multiple diffusions used to fabricate complementary sets of PMOS transistors and NMOS transistors within the circuits. As noted above, a parasitic PNP bipolar transistor may be formed within an n-well CMOS circuit when a source/drain region of a p-channel transistor acts as an emitter, the n-well of the PMOS transistor acts as a base, and a p-type doped substrate acts as the collector. In addition, a parasitic NPN bipolar transistor may be formed within an n-well CMOS circuit when a source/drain region of the n-channel transistor acts as an emitter, a substrate tie of the n-channel transistor acts as a base, and the n-well of the p-channel transistor acts as the collector. The n-type and p-type regions of parasitic bipolar transistors differ slightly for a p-well CMOS circuit in that the p-well acts as a collector of the PNP transistor and the base of the NPN transistor. The n-doped substrate in such a circuit acts as a collector for the NPN transistor and a base for the PNP transistor. As in the n-well CMOS circuit, the source and drain regions of each of the PMOS and NMOS devices respectively serve as the emitters for the PNP and NPN transistors.

Although not shown, the circuit of the PNP and NPN bipolar transistor and resistances Rw and Rs is one of a plurality of devices within CMOS circuits 10, 20, 30 and 40 representing a memory cell array between high voltage source Vcc and low voltage source Vss. Consequently, the current-limiting devices included within circuits 10, 20, 30 and 40 may be used to restrict current through entire memory arrays, rather than just the circuit PNP and NPN bipolar transistor and resistances Rw and Rs shown in FIGS. 1 a-3. In other embodiments, however, the current-limiting devices may be arranged to restrict current through only a subset of memory cells within an array, such as a column or a row of an array or a block of memory cells residing within a plurality of columns and rows.

A pnpn diode structure formed from merged regions of parasitic bipolar transistors is illustrated in FIG. 4. Such a structure may be formed within each of CMOS circuits 10, 20, 30 and 40, since the base and collector regions of the PNP and NPN bipolar transistors are connected. The share regions are referenced in FIG. 4 as n₁ and p₂. In an effort to further explain the phenomenon of latch up, the pnpn diode structure illustrated in FIG. 4 is discussed in conjunction with FIGS. 6 a and 6 b, which illustrate exemplary current-voltage (I-V) plots of pnpn diode structures. The distinction between FIGS. 6 a and 6 b is the inclusion of I-V characteristics for a resistor and a p-channel pass gate transistor, respectively. The use of such I-V characteristics with the I-V plot of a pnpn diode structure is explained in more detail below in reference to FIG. 5. A description of the I-V characteristic of a pnpn diode structure without a description of I-V characteristics for a resistor and a p-channel pass gate transistor, however, is discussed in combination with FIG. 4 to explain its relation to latch up within a CMOS circuit.

As shown in FIG. 4, the pnpn diode structure is interposed between an anode and cathode, which are referenced as voltage sources Vcc and Vss in FIGS. 1 a-3. In addition, three junctions, J₁, J₂, and J₃, are formed in the pnpn diode structure shown in FIG. 4. When there is very little current flow through the pnpn diode structure, the device is referenced as being in an “off,” “forward-blocking,” or “high-impedance” state. In such a state, J₁ and J₃ junctions are weakly forward-biased and junction J₂ is weakly reversed-biased. The I-V characteristic in such a state is represented in the first portion of the pnpn diode I-V plot shown in FIGS. 6 a and 6 b. In particular, the portion of the plot showing current steadily increasing from zero current with increasing voltage represents the “off” state of the device.

The reference of “weakly” biased junctions may generally refer to junctions having a bias which is less than the built-in voltage or potential of the junction. The reference of a “strong” biased junction, however, may conversely refer to a junction which is greater than the built-in voltage or potential of the junction. For example, in some applications, weakly forward biased junctions may refer to junctions which are biased at voltages less than approximately 0.7 V and strongly forward biased junctions may refer to junctions which are biased at voltages greater than approximately 0.7 V. The voltage level for distinguishing weak and strong forward biased junctions, however, may be smaller or larger, depending on the design specifications of the devices comprising the junction. In addition, the voltage level distinguishing weak and strong reversed biased junctions may be different than those for forward bias junctions. In some cases, a strongly biased junction may be strong enough to influence the biasing of an adjacent weakly biased junction, such as in a case when two end junctions of a pnpn diode structure are forward biased enough to forward bias a middle junction of the diode structure as described in more detail below.

As shown in FIGS. 6 a and 6 b, the voltage starts to decrease when the portion of the i-V characteristic reaches a point referred to as the triggering point. The triggering point is denoted in FIGS. 6 a and 6 b as V_(trig) and I_(trig), referring to voltage and current triggering points, respectively. At such a point, junctions J1 and J3 are strongly forward biased due to a regenerative bipolar action wherein part of the npn collector current becomes the pnp base current which is further amplified by the pnp bipolar transistor resulting in a higher pnp collector current. A part of the higher pnp collector current becomes the npn base current which in turn is amplified by the npn bipolar transistor resulting in a higher npn collector current. The iterative increase in pnp and npn collector current inherently increases the forward biasing of the junctions.

After the triggering point, the device exhibits a differential negative resistance (i.e., the voltage sharply decreases as the current slightly increases). During such a portion of the I-V characteristic, the device switches from an “off” state to an “on” state, which is also referred to as a “low-impedance” or “forward conducting” state. In addition, junction J2 is changed from reverse-biased to forward-biased since region p2 in FIG. 4 has a higher potential than region n1. Once the pnpn diode structure is fully transitioned to the “on” state, the current sharply increases and the voltage slightly increases. The point in the I-V plot at which such a change occurs is referenced as the holding level and is denoted in FIGS. 6 a and 6 b as I_(hold) and V_(hold), referring to the current and voltage levels, respectively. If the circuit is able to supply current above the holding level, the device will remain latched in such a state even if the source of the trigger current is removed. Latch up within a CMOS circuit can be caused by a variety of mechanisms, including but not limited to terminal overvoltage stress, transient displacement currents, and ionizing radiation, such as neutron or alpha radiation. The circuits described herein are configured to reduce or eliminate such causes of latch up. In particular, the circuits described herein include a current-limiting device along at least one of the power-supply bus and ground bus of the circuit such that a junction of the pnpn diode structure therein may be maintained as reverse-biased.

Returning to FIGS. 1 a-3, exemplary embodiments of CMOS circuits with currents limiting devices arranged along the power-supply bus or ground bus of the circuits are illustrated. In particular, FIGS. 1 a and 1 b illustrate embodiments in which a current-limiting device is arranged along a power-supply bus of a CMOS circuit. FIG. 1 a illustrates resistor R_(L) formed along power-supply bus 12 of CMOS circuit 10 and FIG. 1 b illustrates p-channel pass gate transistor 26 formed along power-supply bus 22 of CMOS circuit 20. A “pass gate transistor,” as used herein, may generally refer to a transistor having one or both of its source and drain terminals not directly coupled to a power supply of the circuit. Alternatively stated, a pass gate transistor may refer to a transistor having only one or none of its source and drain terminals directly coupled to a power supply of the circuit. In this manner, a pass gate transistor may generally refer to a transistor having at least one of its source and drain terminals that never reaches the potential of the power supply to which it is indirectly coupled. For example, p-channel pass gate transistor 26 in circuit 20 has one node tied directly to voltage source Vcc and another node not directly tied to voltage source Vss. Alternatively, an n-channel pass gate transistor arranged along a ground bus of a circuit, as described in reference to FIGS. 2 and 3 below, may be have a node tied directly to voltage source Vss and another node not directly tied to voltage source Vcc. In yet other cases, the p-channel and n-channel pass gate transistors of the circuits described herein may not have either of their source and drain nodes directly coupled to voltage sources Vcc or Vss.

The resistor and p-channel pass gate transistor included in circuits 10 and 20, respectively, may serve to bleed current from power-supply buses 12 and 22 such that the amount of current drawn through the respective circuits is reduced to a level below a holding current level of a pnpn diode structure in the circuits. In some embodiments, the circuits described herein may include more than on current-limiting device on a power-supply bus and/or a ground bus of the circuit. As such, in some embodiments, CMOS circuit 10 may include multiple resistors arranged along power-supply bus 12. In addition, CMOS circuit 20 may include multiple p-channel pass gate transistors arranged along power-supply bus 22 in some cases. In yet other embodiments, CMOS circuits 10 and or 20 may include a combination of p-channel pass gate transistors and resistors arranged along their power-supply buses.

FIGS. 2 and 3 illustrate alternative embodiments in which CMOS circuits include current-limiting devices along ground buses of the circuits. In particular, FIG. 2 illustrates CMOS circuit 30 having current-limiting device 36 arranged along ground bus 34. In such an embodiment, power-supply 32 of CMOS circuit 30 may be absent of a current limiting device. In other embodiments, however, the circuit described herein may include current-limiting devices along both the power-supply and ground buses of the circuit. For example, FIG. 3 illustrates CMOS circuit 40 including current-limiting devices 46 and 48 arranged along power-supply bus 42 and ground bus 44, respectively. Current-limiting devices 36, 46, and 48 in FIGS. 2 and 3 are shown as blocks to indicate that any type, number, or combination of current-limiting devices may be arranged on the buses of the circuits. In particular, current-limiting devices 36 and 48 in FIGS. 2 and 3 may include one or more resistors and/or one or more n-channel pass gate transistors, and current limiting device 46 may include one or more resistors and/or one or more p-channel pass gate transistors.

In general, the CMOS circuits described in reference to FIGS. 1 a-3 may have current-limiting devices arranged along any portion of their power-supply buses and/or ground buses. For example, one or more current-limiting devices may be arranged along a portion of a power-supply bus which is configured to supply power to all devices within the circuit. More specifically, one or more current-limiting devices may be arranged along a portion of a power-supply bus close to high voltage source Vcc which is configured to supply power to all memory cells within a memory array of the circuit. In other embodiments, one or more current-limiting devices may be additionally or alternatively arranged along a portion of the power-supply bus which supplies current to a subset of memory cells within a circuit. For example, one or more of the current-limiting devices may be arranged along a portion of the power supply bus which supplies current to a single column or row of a memory array of CMOS transistors. In addition or alternatively, one or more current-limiting devices may be arranged along portions of the power-supply bus configured to supply current to a block of memory cells residing in a plurality of columns and rows. The portions of the power-supply bus supplying power to subsets of memory cells may be portions partitioned from the portion of the power-supply bus near high voltage source Vcc supplying current to all devices within the circuit.

One advantage of arranging a current-limiting device along a portion of the power supply bus which supplies current to one or two columns and/or rows of a memory array is that the reliability degradation of redundancy repaired memory arrays is reduced. Redundancy within a memory array involves the creation of spare rows and columns which can be used as substitutes for production rows and columns, which are found to be defective. Additional circuitry is also provided within a memory array to control the physical encoding that enables the substitution of a spare column or row for a defective column or row. The concept of row redundancy repair involves replacing bad bit lines or word lines with good bit line or word lines, respectively. The column or row to be repaired is not physically replaced, but rather it is logically replaced. In particular, whenever a column or row address is called, the address is compared to the addresses of known bad column or rows. If the address comparison produces a match, then a replacement bit line or word line is fired in place of the defect bit line or word line.

As noted above, methods for preventing latch up in conventional memory array circuits is to incorporate well regions or contacts within each memory cell of the memory array. Since the fabrication of well regions and contacts are process sensitive, the likelihood of latch up within an array varies between memory cells. As a result, a reliability risk exists when repairing memory arrays through redundancy. The circuits described herein preferably eliminate the likelihood of latch up within memory cells or at least reduce the likelihood of latch up to be substantially similar throughout an array. As a result, reliability degradation of redundancy repaired memory cells will be reduced Embodiments having a current-limiting device for every one or two columns or rows of the array, including the spare columns and rows, may particularly reduce reliability degradation of redundancy repaired memory cells.

Ground bus lines are often configured in a grid pattern in order to serve as the negative power source with which to induce current through a plurality of devices within a circuit. Consequently, one or more current-limiting devices may be arranged along any portion of a ground bus and have substantially the same impact on preventing latch up within the circuit than if the current-limiting devices were arranged along another portion of the ground bus. In embodiments in which a ground line is not arranged in a grid pattern, however, the arrangement of current-limiting devices along the ground line may be specific to restricting current through a subset of devices within the circuit in some cases. In any case, one or more current-limiting devices may be additionally or alternatively arranged along a portion of the ground line close to low voltage source Vss such that current is restricted through all devices within the circuit.

As noted above, the circuits described herein may include one or more current-limiting devices. In particular, the circuits may include one or more current limiting devices arranged along the same portion of a power-supply bus or ground bus. In other embodiments, the circuit may include one or more current limiting devices arranged along a plurality of different portions of a power-supply bus and/or ground bus. In addition, in embodiments in which a plurality of current-limiting devices are arranged along a power-supply bus and/or ground bus of a circuit, the current-limiting devices included may be similarly or differently sized. In particular, the current-limiting devices may be configured to restrict similar amounts of current or different amounts of current. In some cases, the number, size and placement of current-limiting devices may be optimized for different portions of a circuit.

As noted above, in addition to showing I-V characteristics of a pnpn diode structure, FIGS. 6 a and 6 b illustrate I-V characteristics of a resistor and a pass gate transistor, respectively. Such lines may be used to size a current-limiting device such that latch up may be prevented in a circuit. Alternatively stated, correlating I-V characteristics of a pnpn diode structure and a resistor and/or pass gate transistor may allow a circuit to be designed with a current-limiting device sufficient to maintain a junction of the pnpn diode structure as reversed-biased. In this manner, a current-limiting device may be referred to as being “configured” to prevent latch up within a memory cell. A flowchart of a method outlining such a design process is illustrated in FIG. 5 and is discussed in conjunction with FIGS. 6 a and 6 b. As shown in FIG. 5, the method may include block 50 in which an I-V plot of a pnpn diode structure arranged within a CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit is created. Although I-V plots of pnpn diode structures may vary slightly depending on the design characteristics of the device in which they are arranged, the basic shape and points of interests, such as the triggering point and holding points, remain substantially the same. As such, the I-V characteristics of a pnpn diode structure discussed above relative to FIGS. 6 a and 6 b may correlate to the I-V plot referenced in block 50. The formation of the I-V plot referenced in block 50 may preferably be obtained by a simulation program, but may alternatively be obtained by manual means.

As shown in FIG. 5, the method may continue to block 52 to determine a holding current level of the pnpn diode structure from the I-V plot created in block 50. As noted above, the holding current level may refer to the level of current which is sufficient to keep a circuit latched even after a triggering current is removed. Such a level is referred to as I_(hold) in FIGS. 6 a and 6 b. The method continues in FIG. 5 to block 54 in which a current-limiting device to be placed along a power bus of a second CMOS circuit having similar design specifications as the CMOS circuit used to create the I-V plot referenced in block 50 is sized such that the current through the second CMOS circuit does not exceed the holding current level of a pnpn diode structure within the circuit. Such a step may include selecting a current-limiting device having an I-V characteristic which intersects the I-V plot of the pnpn diode structure at a level below the holding current level. The selection may be conducted by plotting the I-V characteristic of an exemplary current-limiting device to determine if the line intersects the current-voltage plot of the pnpn diode structure at a level below the holding current level. Such plotting may be conducted using a simulation program or may be done manually. In embodiments in which multiple current-limiting devices are arranged along power bus of a CMOS device, an I-V characteristic which is representative of the combination of current-limiting devices may be plotted along with the I-V characteristic of the pnpn diode structure. In this manner, the current-limiting devices may be sized such that an I-V characteristic of a combination of the devices intersect the current-voltage plot of the pnpn diode structure at a level below the holding current level.

In some cases, the method may include sizing the current-limiting device to be placed along the power bus of the second CMOS circuit such that the current through the second CMOS circuit does not exceed the trigger current level of the I-V plot of the pnpn diode structure. Such a step may include selecting a current-limiting device having an I-V characteristic which intersects the I-V plot of the pnpn diode structure at a level below the trigger current level as shown in FIGS. 6 a and 6 b. As with selecting a current-limiting device having an I-V characteristic which intersects the I-V plot of the pnpn diode structure at a level below the holding current level, the selection of a current-limiting having an I-V characteristic which intersects the I-V plot of the pnpn diode structure at a level below the trigger current level may include sizing a single current-limiting device or multiple current-limiting devices.

It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to provide CMOS circuit which is configured to prevent latch up without increasing memory cell size. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. For example, the circuit and method described herein may be incorporated into any memory device comprising CMOS transistors. In addition, the circuits described herein may include any other methods for reducing and/or eliminating latch-up with memory cells. In particular, the circuits described herein may additionally include well regions and/or substrate and well contacts to prevent the phenomenon of latch up within memory cells. It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. 

1. An electronic circuit comprising: a complimentary-metal-oxide-semiconductor (CMOS) circuit coupled to a power-supply bus; and a p-type field-effect-transistor (PFET) coupled to said power-supply bus and to one or more columns of memory cells of a memory cell array and configured to limit current supplied to said one or more columns of memory cells to a magnitude less than a trigger current level of said CMOS circuit.
 2. The electronic circuit of claim 1 further comprising an n-type field-effect-transistor (NFET) coupled to a ground bus and said one or more columns of memory cells and configured to limit current sunk from said one or more columns of memory cells to a magnitude less than the trigger level of said CMOS circuit.
 3. The electronic circuit of claim 1 wherein said PFET is coupled to Vcc.
 4. The electronic circuit of claim 2 wherein said NFET is coupled to Vss.
 5. The electronic circuit of claim 1 wherein the magnitude of a column supply current is controlled by said PFET.
 6. An electronic circuit comprising: a first CMOS circuit coupled to an array of memory cells and to a power-supply bus; and a first PFET coupled to a first segment of said power-supply bus and to said first CMOS circuit, wherein said first segment is configured to provide power to a first subset of memory cells of said array of memory cells and wherein said first PFET is configured to limit current supplied on said power-supply bus to a magnitude which is less than a trigger current level of said first CMOS circuit.
 7. The electronic circuit of claim 6 wherein said power-supply bus is coupled to Vcc.
 8. The electronic circuit of claim 6 wherein said power-supply bus is coupled to Vss.
 9. The electronic circuit of claim 6 wherein a magnitude of a column select current supplied to the subset of memory cells is controlled by said PFET.
 10. The electronic circuit of claim 6 further comprising: a second CMOS circuit coupled to said array of memory cells; and a second PFET coupled to said power-supply bus, wherein said second PFET is configured to limit current supplied to said second CMOS circuit
 11. The electronic circuit of claim 10 wherein said first PFET and said second PFET are configured to restrict different amounts of current.
 12. The electronic circuit of claim 10 wherein said second PFET is coupled to a second segment of said power-supply bus and said second segment is configured to provide power to all of said memory cells of said array of memory cells.
 13. The electronic circuit of claim 10 wherein said second PFET is coupled to a second segment of said power-supply bus and said second segment is configured to provide power to a second subset of memory cells of said array of memory cells that is distinct from said first subset of memory cells.
 14. A static random access memory (SRAM) comprising: data input/output circuitry; CMOS circuitry coupled to said data input/output circuitry; a memory cell array coupled to said CMOS circuitry wherein said memory cell array comprises a plurality of rows and columns of memory cells; and a PFET coupled to one or more of said plurality of rows and columns of memory cells, wherein said PFET is configured to limit current supplied to said CMOS circuitry to a magnitude that is less than a trigger current level of said CMOS circuitry.
 15. The SRAM of claim 14 further comprising an n-type field-effect-transistor (NFET) coupled to said one or more said plurality of rows and columns of memory cells and configured to limit current sunk from said one or more said plurality of rows and columns of memory cells to a magnitude less than a trigger level of said CMOS circuit.
 16. The SRAM of claim 14 wherein said PFET is coupled to said one or more said plurality of rows and columns of memory cells at Vcc.
 17. The SRAM of claim 15 wherein said NFET is coupled to said one or more said plurality of columns of memory cells at Vss.
 18. The SRAM of claim 14 wherein a magnitude of a column select current supplied to said one or more of said plurality of columns is controlled by said PFET. 